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SLS System Logic Semiconductor
SL20T0081
81 COMMON x 132 SEGMENT STN LCD DRIVER / CONTROLLER
SL20T0081
SLS System Logic Semiconductor
SL20T0081
DEVICE SPECIFICATION
OVERVIEW
INTRODUCTION
The SL20T0081 is a single-chip graphic dot-matrix liquid crystal display driver & controller that can be connected directly to a microprocessor bus. 8-bit parallel or serial display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a liquid crystal drive signal independent of the micro-processor. The SL20T0081 contains 81x132 bits of display data RAM and there is a 1-to-1 correspondence between the liquid crystal panel pixels and the internal RAM bits, and the device contains 81 common output circuits and 132 segment output circuits, so that a single chip can drive a 81x132 dot display (capable of displaying 8 columns x 5 rows of a 16 x 16 dot font). Moreover, the capacity of the display can be extended through the use of master/ slave structures between chips. The chips are able to minimize power consumption because no external operating clock is necessary for the display data RAM read/write operation. Furthermore, because each chip is equipped internally with a low-power liquid crystal driver power supply, resistors for liquid crystal driver power voltage adjustment and a display clock RC oscillator circuit, the SL20T0081 Series chips can be used to create the lowest power display system with the fewest components for high performance portable systems.
FEATURES
Direct display of RAM data through the display data RAM. RAM capacity : 81x132 = 8580 bits Table 1. Duty and Bias selection Duty 1/81 1/65 1/55 1/49 1/33 RAM bit data : LCD Driver Bias 1/10 or 1/8 1/9 or 1/7 1/8 or 1/6 1/8 or 1/6 1/6 or 1/5 "1" Non-illuminated "0" illuminated (during normal display) Maximum display matrix 81 x 132 65 x 132 55 x 132 49 x 132 33 x 132
High-speed 8-bit MPU interface The chip can be connected directly to the both the 80x86 series MPUs and the 68000 series MPUs. Serial interface available (supports write operation only). Abundant command functions Display data Read/Write,display ON/OFF, Normal/Reverse display mode, page address set, display start line set, column address set, status read, display all point ON/OFF, LCD bias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, common output status select, V5 voltage regulation internal resistor ratio set. Static drive circuit equipped internally for indicators 1 driver, with 4 kinds of flashing mode
SLS System Logic Semiconductor
SL20T0081
Built-in Power Supply Circuit Low-power liquid crystal display power supply circuit equipped internally. Booster circuit (with Boost ratios of x2 / x3 / x4 / x5, where the step-up voltage reference power supply can be input externally). o High-accuracy voltage adjustment circuit (Thermal gradient -0.05%/ C or external input). LCD driver voltage regulator resistors and voltage followers equipped internally. RC oscillator circuit equipped internally (external clock can also be selected). Operating Voltage Range Supply Voltage (VDD) : 2.4V ~ 3.6V LCD driver Voltage (VLCD) : 4.5V ~ 16.0V Low Power Consumption Operating power Standby power
: 40uA typical (conditions:VDD =3V, x 4 boosting (VCI = VDD ), V0 =11V, Internal power supply ON,display OFF and normal mode is selected ) : 10uA maximum (during power save [standby] mode)
Operating Temperatures o Wide range of operating temperatures : -40 to 85 C CMOS Process Package Type TCP
SLS System Logic Semiconductor
BLOCKDIAGRAM
SL20T0081
SEG131
COM39
COM40
COM79
COM0
VDD
VSS V0 V1 V2 V3 V4 COM Drivers SEG Drivers COM Drivers COMS
CAP1+ CAP1CAP2+ CAP2CAP3+ CAP4+ VOUT VCI VEXT VR IREF IRE HPMB Power Supply Circuit
Display Data Read Circuit FR FRS Row Address Decoder SYNC Timing Generation & Read/Write Circuit CL DISP MS DUTY0 DUTY1 DUTY2 Oscillation Circuit
Display Data Memory 81 x 132 bits
Column Address Decoder
COMS
SEG0
CLS
Command Decoder
Status
MPU Interface
WR (R/W)
D6 (SCK)
RESET
P68/86
D7 (SI)
RD (E)
CE1
CE2
RS
PS
D5
D4
D3
D2
D1
D0
SLS System Logic Semiconductor
PAD CONFIGURATION
PAD Layout
Figure 1. SL20T0081 PAD Layout
282 283 147
SL20T0081
146
Y X
(0,0)
325 104
1
103
Table 2. SL20T0081 PAD Dimensions Item Chip Size Pad No. X 2 to10, 94 to 102, 104 to 146, 148 to 281, 283 to 325 11 to 41, 45-46, 50 to 93 Pad pitch 41-42, 44-45, 46-47, 49-50 42 to 44, 47 to 49 1-2, 102-103, 147-148, 281-282 10-11, 93-94 2 to 10, 94 to 102, 148 to 281 104 to 146, 283 to 325 Bumped PAD size (Bottom) 11 to 41, 45, 46, 50 to 93 42 to 44, 47 to 49 1, 103, 147, 282 Bumped PAD height Figure 2. Align Key Coordination COG Align Key Coordination
30m 30m 30m 30m 30m 30m
Size Y 3000 60 80 110 120 131 90 37 92 57 67 72 18 92 37 92 92 97
Unit
8900
m
All PAD
ILB Align Key Coordination
60m
Potting Mark Coordination
72m
30m 30m 30m
(-4230.0, -1415.0)
30m
60m
(4230.0, -1430.0)
upper left : (-4365.0, 1415.0) lower right : (4365.0, -1415.0)
(4346.0, 1406.0)
SLS System Logic Semiconductor
SL20T0081
PAD CENTER COORDINATES
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 PAD name DUMMY5 DUMMY6 DUMMY7 DUMMY8 DUMMY9 DUMMY10 DUMMY11 DUMMY12 DUMMY13 DUMMY14 FRS FR SYNC CL DISP VDD VSS CE1 CE2 VDD RESETB RS VSS WR(R/W) RD(E) VDD D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> VSS VDD DUTY0 DUTY1 VDD VSS DUTY2 VDD VDD VDD VCI VCI VSS VSS VSS VOUT VOUT CAP4+ CAP4+ CAP3+ CAP3+ CAP1X -4121 -3990 -3930 -3870 -3810 -3750 -3690 -3630 -3570 -3510 -3420 -3340 -3260 -3180 -3100 -3020 -2940 -2860 -2780 -2700 -2620 -2540 -2460 -2380 -2300 -2220 -2140 -2060 -1980 -1900 -1820 -1740 -1660 -1580 -1500 -1420 -1340 -1260 -1180 -1100 -1020 -910 -790 -670 -560 -480 -370 -250 -130 -20 60 140 220 300 380 460 Y -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 PAD No. 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 PAD name CAP1CAP1+ CAP1+ CAP2+ CAP2+ CAP2CAP2VDD VEXT IREF TEST_VREF VSS V1 V1 V2 V2 V3 V3 V4 V4 V0 V0 VR VR VSS VSS VDD MS CLS VSS P68/80 PS VDD HPMB VSS IRE VDD TRCON VSS TRIM<4> TRIM<3> VSS TRIM<2> TRIM<1> VSS TRIM<0> DUMMY15 DUMMY16 COM<39> COM<38> COM<37> COM<36> COM<35> COM<34> COM<33> COM<32> X 540 620 700 780 860 940 1020 1100 1180 1260 1340 1420 1500 1580 1660 1740 1820 1900 1980 2060 2140 2220 2300 2380 2460 2540 2620 2700 2780 2860 2940 3020 3100 3180 3260 3340 3420 3510 3570 3630 3690 3750 3810 3870 3930 3990 4121 4361 4361 4361 4361 4361 4361 4361 4361 4361 Y -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1411 -1250 -1190 -1130 -1070 -1010 -950 -890 -830 -770
SLS System Logic Semiconductor
SL20T0081
PAD CENTER COODINATES (continued)
PAD No. 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 PAD name COM<31> COM<30> COM<29> COM<28> COM<27> COM<26> COM<25> COM<24> COM<23> COM<22> COM<21> COM<20> COM<19> COM<18> COM<17> COM<16> COM<15> COM<14> COM<13> COM<12> COM<11> COM<10> COM<9> COM<8> COM<7> COM<6> COM<5> COM<4> COM<3> COM<2> COM<1> COM<0> COMSR DUMMY17 DUMMY18 DUMMY19 SEG<0> SEG<1> SEG<2> SEG<3> SEG<4> SEG<5> SEG<6> SEG<7> SEG<8> SEG<9> SEG<10> SEG<11> SEG<12> SEG<13> SEG<14> SEG<15> SEG<16> SEG<17> SEG<18> SEG<19> X 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4361 4121 3990 3930 3870 3810 3750 3690 3630 3570 3510 3450 3390 3330 3270 3210 3150 3090 3030 2970 2910 2850 2790 Y -710 -650 -590 -530 -470 -410 -350 -290 -230 -170 -110 -50 10 70 130 190 250 310 370 430 490 550 610 670 730 790 850 910 970 1030 1090 1150 1210 1270 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 PAD No. 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 PAD name SEG<20> SEG<21> SEG<22> SEG<23> SEG<24> SEG<25> SEG<26> SEG<27> SEG<28> SEG<29> SEG<30> SEG<31> SEG<32> SEG<33> SEG<34> SEG<35> SEG<36> SEG<37> SEG<38> SEG<39> SEG<40> SEG<41> SEG<42> SEG<43> SEG<44> SEG<45> SEG<46> SEG<47> SEG<48> SEG<49> SEG<50> SEG<51> SEG<52> SEG<53> SEG<54> SEG<55> SEG<56> SEG<57> SEG<58> SEG<59> SEG<60> SEG<61> SEG<62> SEG<63> SEG<64> SEG<65> SEG<66> SEG<67> SEG<68> SEG<69> SEG<70> SEG<71> SEG<72> SEG<73> SEG<74> SEG<75> X 2730 2670 2610 2550 2490 2430 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 810 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -510 -570 Y 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411
SLS System Logic Semiconductor
SL20T0081
PAD CENTER COODINATES (continued)
PAD No. 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 PAD name SEG<76> SEG<77> SEG<78> SEG<79> SEG<80> SEG<81> SEG<82> SEG<83> SEG<84> SEG<85> SEG<86> SEG<87> SEG<88> SEG<89> SEG<90> SEG<91> SEG<92> SEG<93> SEG<94> SEG<95> SEG<96> SEG<97> SEG<98> SEG<99> SEG<100> SEG<101> SEG<102> SEG<103> SEG<104> SEG<105> SEG<106> SEG<107> SEG<108> SEG<109> SEG<110> SEG<111> SEG<112> SEG<113> SEG<114> SEG<115> SEG<116> SEG<117> SEG<118> SEG<119> SEG<120> SEG<121> SEG<122> SEG<123> SEG<124> SEG<125> SEG<126> SEG<127> SEG<128> SEG<129> SEG<130> SEG<131> X -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 -2190 -2250 -2310 -2370 -2430 -2490 -2550 -2610 -2670 -2730 -2790 -2850 -2910 -2970 -3030 -3090 -3150 -3210 -3270 -3330 -3390 -3450 -3510 -3570 -3630 -3690 -3750 -3810 -3870 -3930 Y 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 1411 PAD No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 PAD name DUMMY1 DUMMY2 DUMMY3 COM<40> COM<41> COM<42> COM<43> COM<44> COM<45> COM<46> COM<47> COM<48> COM<49> COM<50> COM<51> COM<52> COM<53> COM<54> COM<55> COM<56> COM<57> COM<58> COM<59> COM<60> COM<61> COM<62> COM<63> COM<64> COM<65> COM<66> COM<67> COM<68> COM<69> COM<70> COM<71> COM<72> COM<73> COM<74> COM<75> COM<76> COM<77> COM<78> COM<79> COMSL DUMMY4 X -3990 -4121 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 -4361 Y 1411 1411 1270 1210 1150 1090 1030 970 910 850 790 730 670 610 550 490 430 370 310 250 190 130 70 10 -50 -110 -170 -230 -290 -350 -410 -470 -530 -590 -650 -710 -770 -830 -890 -950 -1010 -1070 -1130 -1190 -1250
SLS System Logic Semiconductor
PIN DESCRIPTION
Power Supply Pins
Pin Name VDD VSS VCI V0 V1 V2 V3 V4 I/O Power Supply Power Supply Power Supply Positive Power Supply. System Ground. Function
SL20T0081
Voltage Booster input pin. The power supply for the voltage booster. VCI input voltage is the reference of boosted output voltage (VOUT) of voltage booster. LCD driver supply voltage pins. When the internal LCD power supply circuit is enabled, these voltages are generated by it. When the internal LCD power supply circuit is disabled, these voltages must be supplied externally, and they should have the following relationship. VSS < V4 < V3 < V2 < V1 < V0
Power Supply
LCD Power Supply Circuit Pins
Pin Name CAP1+ CAP1CAP2+ CAP2CAP3+ CAP4+ VOUT VEXT I/O O O O O O O O I Function Voltage booster pin. Connect a capacitor between this pin and the CAP1- pin Voltage booster pin. Connect a capacitor between this pin and the CAP1+ pin Voltage booster pin. Connect a capacitor between this pin and the CAP2- pin Voltage booster pin. Connect a capacitor between this pin and the CAP2+ pin Voltage booster pin. (refer the application example to connecting a capacitor) Voltage booster pin. (refer the application example to connecting a capacitor) Voltage booster pin. Connect a capacitor between this pin and VSS. This is the external reference voltage input pin of the LCD power supply circuit. This pin is valid only when internal reference voltage circuit is disabled (IREF=0). Internal reference voltage circuit enable pin. IREF = 0 : Internal reference voltage circuit is disabled. External reference voltage is inputted via VEXT pin. IREF = 1 : Internal reference voltage circuit is enabled. External V0 voltage adjustment pin. VR pin is valid only when the internal voltage regulator resistors are not used (IRE=0) Internal voltage regulator resistor enable pin. This pin selects the resistors for the V0 voltage level adjustment. IRE = 1 : Use the internal resistors IRE = 0 : Do not use the internal resistors. The V0 voltage level is controlled by the external resisters that connected among V0 pin and VR pin and VSS.
IREF
I
VR
I
IRE
I
SLS System Logic Semiconductor
SL20T0081
System Control pins
Pin Name I/O Function This pin selects the master/slave operation for the SL20T0081 chip. Master operation outputs the timing signals that are required for the LCD display, while slave operation inputs the timing signals required for the liquid crystal display. MS = 1 : Master operation MS = 0 : Slave operation Following table shows difference of the master operation and the slave operation. MS I MS 1 0 CLS 1 0 Internal Oscillator Circuit Enabled Disabled Disabled Internal Power Supply Circuit Enabled Enabled Disabled CL Output Input Input SYNC Output Output Input DISP Output Output Input
CL
I/O
This is the display clock input/output pin. When multiple SL20T0081 chips are used in master/slave mode, all of CL pins must be connected each other. Internal RC oscillator enable pin. CLS = 1 : Internal oscillator circuit is enabled. CLS = 0 : Internal oscillator circuit is disabled. When CLS=0, the display clock must be inputted through the CL pin. This pin is valid only when SL20T0081 operating in master operation. LCD synchronization signal input/output pin. When multiple SL20T0081 chips are used in master/slave mode, all of SYNC pins must be connected each other. This is the liquid crystal display blanking control pin. When multiple SL20T0081 chips are used in master/slave mode, all of DISP pins must be connected each other. The LCD driver duty ratio selection pins. DUTY2 DUTY1 DUTY0 1 1 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0
CLS
I
SYNC
I/O
DISP
I/O
DUTY0 DUTY1 DUTY2
I
Duty ratio 1/81 1/81 1/65 1/55 1/49 1/33
Common Output Even, Odd normal " " " "
When Duty = (1, 1, 1), 1/81 duty ratio is selected, and common output pin configuration is changed. At this mode, all even numbered common output pins are outputting right side of the device and all odd numbered common output pins are outputting left side of the device. This is the power control pin for the power supply circuit for liquid crystal drive. HPMB = 1 : Normal mode HPMB = 0 : High power mode This pin is enabled only when the master operation mode is selected. It is fixed to either 0 or 1 when the slave operation mode is selected.
HPMB
I
SLS System Logic Semiconductor
SL20T0081
System Interface pins
Pin Name RESET I/O I Function Device Reset pin. When RESET = 0, device initialization operation is executed. 8bit bi-directional data bus that should be connected to the standard MPU data bus. When PS=0 the serial interface is enabled and pins are set as following. D7 : Serial data input (SI) D6 : Serial interface clock input (SCK) D5 ~ D0 : high impedance state When the chip does not be selected, D7 ~ D0 are set to high impedance. Display data / Control data selection signal input pin RS = 1 : D7 ~ D0 input are display data RS = 0 : D7 ~ D0 input are control data Chip Select signal input pins When CE1 = 0 and CE2 = 1, then the chip select becomes active, and data/command I/O is enabled. * When the device connected to an 8080 MPU bus, this pin acts as "active LOW" read signal input pin. If the device is selected and RD = 0, then SL20T0081 outputs the data to data bus pins. * When the device connected to a 6800 MPU bus, this pin acts as "active HIGH" R/W enable signal input pin. If the device is selected and RD = 1, then SL20T0081 executes read or write operation that controlled by WR signal. * When the device connected to an 8080 MPU bus, this pin acts as "active LOW" write signal input pin. If the device is selected and WR = 0, then SL20T0081 accepts the data via data bus pins. * When the device connected to a 6800 MPU bus, this pin acts as read/write control signal input pin. WR(R/W) = 1 : Read WR(R/W) = 0 : Write Bus type selection pin. P68/80 = 1 : 6800 MPU bus type interface. P68/80 = 0 : 8080 MPU bus type interface Parallel data transfer / Serial data transfer mode selection pin. PS = 1 : Parallel data transfer mode. PS = 0 : Serial data transfer mode. PS I PS 1 0 Data transfer mode Parallel data transfer Serial data transfer Read enabled disabled Write enabled enabled Data bus D7 ~D0 D7 (SI) SCK pin D6 (SCK)
D7 ~ D0 (SI) (SCK) I/O
RS
I
CE1 CE2
I
RD (E)
I
WR (R/W)
I
P68/80
I
When PS = 0, RD(E) and WR(R/W) pins are fixed to either 0 or 1.
SLS System Logic Semiconductor
SL20T0081
Liquid Crystal Drive Pins
Pin Name I/O Function LCD segment driver output pins. Segment driver output voltage is controlled by display data and FR signal. SEG0 ~ SEG131 Display data O 1 1 0 0 Power save FR 1 0 1 0 Segment driver output voltage Normal Display Reverse Display V0 V2 VSS V3 V2 V0 V3 VSS VSS
LCD common driver output pins. Common driver output voltage is controlled by internal scanning data and FR signal. COM0 ~ COM79 Scan Data O FR Common driver output voltage VSS V0 V1 V4 VSS
1 1 1 0 0 1 0 0 Power save mode
COMS(R) COMS(L) FR FRS
O
Common drive output for the icons. There are two COMS pin, COMS(R), COMS(L). They output same signal. When in master/slave mode, the same signal is output by both master and slave. Static segment driver output pin. This pin is paired with FRS pin. Static segment driver output pin. This pin is paired with FR pin.
O O
SLS System Logic Semiconductor
FUNCTION DESCRIPTION
MICROPROCESSOR INTERFACE
SL20T0081
Chip Select Input There are CE1 and CE2 pins for chip selection. The SL20T0081 can interface with an MPU only when CE1 is "L" and CE2 is "H". When these pins are set to any other combination, RS, RDB(E) and_WRB(RW) inputs are disabled and D0to D7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface SL20T0081 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or serial inter face is determined by PS pin. Table 3. Parallel / Serial Interface Mode PS H L Type Parallel Serial CE1 CE1 CE1 CE2 CE2 L CE2
*x
P68/80 H
Interface mode 6800-series MPU mode 8080-series MPU mode Serial-mode
*x
:Don't care
Parallel Interface (PS = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by P68/80 as shown in table 4. The type of data transfer is determined by signals at RS, RD(E) and WR(R/W) as shown in table 5. Table 4. Microprocessor Selection for Parallel Interface P68/80 H L CE1 CE1 CE1 CE2 CE2 CE2 RS RS RS RD(E) E RD WR(R/W) R/W WR D0 to D7 D0 to D7 D0 to D7 MPU bus 6800-series 8080-series
Table 5. Parallel Data Transfer Common RS H H L L 6800-series RD (E) H H H H WR (R/W) H L H L 8080-series Description RD L H L H WR H L H L Display data read out Display data write Register status read Writes to internal register (instruction)
SLS System Logic Semiconductor
SL20T0081
Serial Interface (PS = "L") When the SL20T0081 is active, serial data (D7) and serial clock (D6) input are enabled. And not active,the internal 8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock going into D6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data when RS is high and caused by the line length, the operation check on the actual machine is recommended. Figure 3. Serial Interface Timing CE1 CE2 SID SCLK RS D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4
Busy Flag The Busy Flag indicates whether the SL20T0081 is operating or not. When D7 is "H" in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance.
SLS System Logic Semiconductor
SL20T0081
Data Transfer The SL20T0081 used bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to internal RAM, data is automatically transferred the bus holder to the RAM as shown in figure 4. And when reading data from internal RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. Figure 4. Write Timing MPU signals RS WR D7 ~ D0 Internal signals WR BUS HOLDER COLUMN ADDRESS N N D(N) D(N+1) N+1 D(N+2) N+2 D(N+3) N+3 N+4 N D(N) D(N+1) D(N+2) D(N+3)
SLS System Logic Semiconductor
SL20T0081
Figure 5. Read Timing MPU signals RS WR RD D7 ~ D0 N Dummy D(N) D(N+1) D(N+2)
Internal signals WR RD BUS HOLDER COLUMN ADDRESS N N D(N) N+1 D(N+1) N+2 D(N+2) N+3 D(N+3) N+4
SLS System Logic Semiconductor
SL20T0081
LCD DISPLAY CIRCUIT
Display Data RAM The Display Data RAM stores pixel data for the LCD. It is 81-row by 132-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 81 row are divided into 10 pages of 8 lines and the 11th page with a single line (D0 only). Data is read from or written to the 8 lines of each page directly through D7 to D0. The display data of D7 to D0 from the microprocessor correspond to the LCD common lines as shown in figure 6. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker. Figure 6. Display Data RAM to LCD panel Data Transfer 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 0 0
DB0 DB1 DB2 DB3 DB4
COM0 COM1 COM2 COM3 COM4 LCD panel
Display Data RAM
Page Address Circuit This circuit is for providing a Page Address to Display Data RAM show in figure 6. It incorporates 4-bit Page Address register changed by only the "Set Page" instruction. Page Address 11 is a special RAM area for the icons and display dataD0 is only valid. When Page Address is above 8, it is impossible to access to Display Data RAM. Line Address Circuit This circuit assigns Display Data RAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of Display Data RAM as shown in figure 6. It incorporates 7-bit line address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the Line Address for transferring the 132-bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the MPU can not access Line Address of icons.
SLS System Logic Semiconductor
SL20T0081
Column Address Circuit Column Address circuit has an 8-bit preset counter that provides column address to the Display Data RAM as show in figure 7. When Set Column Address MSB/LSB instruction is issued, 8-bit [Y7:Y0] is updated. And, since this address is increased by 1 each or write data instruction, microprocessor can access the display data continuously. However, the counter is not increased and locked if a non-existing address above 84H. It is unlocked if a column address is set again by set Column Address MSB/LSB instruction. And the Column Address counter is independent of page address register. ADC Select instruction makes it possible to invert the relationship between the Column Address and the segment outputs.It is necessary to rewrite the display data on built-in RAM after issuing ADC select instruction. Refer to the following figure 7. Figure 7. The Relationship between Column Address and Segment output SEG 0 00H 1 SEG 1 01H 0 SEG 2 02H 1 SEG 3 03H 1 SEG 4 04H 0 SEG 127 7FH 1 SEG 128 80H 0 SEG 129 81H 0 SEG 130 82H 1 SEG 131 83H 0
SEG Output Column Address Display Data LCD panel
ADC = 0
ADC = 1
Segment Control Circuit
This circuit controls the display data by the display ON/OFF, reverse display ON/OFF and entire display ON/OFF instructions without changing the data in display data RAM.
SLS System Logic Semiconductor
Figure 8. Display Data RAM Map (1/81, 1/65 duty mode)
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 1/81 Duty 1/65 Duty
SL20T0081
0
0
0
0
Page0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
1
0
0
0
Page 8
1
0
0
1
Page 9
1
0
1
0
Page 10
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COMS
Column Address
ADC=0 ADC=1
00 83 SEG0
01 82 SEG1
02 81 SEG2
03 80 SEG3
04
05
06
-------
7D 7E 7F 80 06 SEG125 05 SEG126 04 SEG127 03 SEG128
81 02 SEG129
82 01 SEG130
83 00 SEG131
7F 7E 7D SEG4 SEG5 SEG6
LCD Output
----
Example of when initial display start line address is 1CH.
SLS System Logic Semiconductor
SL20T0081
Oscillator This is completely on-chip oscillator and its frequency is nearly independent of VDD. This oscillator signal is used in the voltage converter and display timing generation circuit. The oscillator circuit is only enabled when MS="H' and CLS="H". When on-chip oscillator is not used, CLS pin must be "L"condition. In this time, external clock must be input from CL pin. Display Timing Generator Circuit This circuit generates some signals to be used for displaying LCD. The display clock, CL generated by oscillation clock, generates a clock to the line counter and a latch signal to the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock (CL) and the 132-bit display data is latched by the display data latch circuit in synchronization with display clock. The display data which is read to the LCD driver is completely independent of the access to the display data RAM from the microprocessor. The LCD AC signal, SYNC is generated from the display clock. 2-frame AC driver waveforms with internal timing signal are shown in figure 8. In a multiple chip configuration, the slave chip requires the SYNC, CL and DISP signals from the master. Table 6 shows the SYNC, CL, and DISP status. Table 6. Master and Slave Timing Signal Status Operation mode Master OFF(external clock used) Slave Output Input Input Input Output Input Oscillator ON(internal clock used) SYNC Output CL Output DISP Output
SLS System Logic Semiconductor
SL20T0081
Common Output Control Circuit This circuit controls the relationship between the number of common output and specified duty ratio. SHL select instruction specifies the scanning direction of the common output pins. Table 7. The Relationship between Duty Ratio and Common Output
Common output pins Duty SHL COM 0 ~ 15 COM 0 ~ 15 COM 31 ~ 16 COM 16 ~ 23 COM 24 ~ 26 COM 27 ~ 31 COM 32 ~ 39 COM 40 ~ 47 COM 48 ~ 52 COM 53 ~ 55 COM 56 ~ 63 COM 64 ~ 79 COM 16 ~ 31 COM 15 ~ 0 COMS
0 1/33 1 0 1/49 1 0 1/55 1 0 1/65 1 0 1/81 1
NC*1 NC*1 NC*1 NC*1 NC*1 NC*1 NC*1 NC*1 COM 0 ~ COM79 COM 79 ~ COM0 NC*1
COM0 ~ COM23 COM47 ~ COM24 COM0 ~ COM26 COM53 ~ COM27 COM0 ~ COM31 COM63 ~ COM32
COM24 ~ COM47 COM23 ~ COM0 COM27 ~ COM53 COMS COM26 ~ COM0 COM32 ~ COM63 COM31 ~ COM0
: NO Connection
SLS System Logic Semiconductor
SL20T0081
POWER SUPPLY CIRCUITS
The Power Supply circuits generate the voltage levels necessary to driver liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are valid only in master operation and controlled by power control instruction . For details, refers to "Instruction Description". Table 8 shows the referenced combinations in using Power Supply circuits. Table 8. Recommended Power Supply Combinations User Setup Only the internal power supply circuits are used Only the voltage regulator circuits and voltage follower circuits are used Only the voltage follower circuits are used Only the external power supply circuits are used Power control (VC VR VF) 111 V/C circuits ON V/R circuits ON V/F circuits ON VOUT V0 V1 to V4
Open
Open
Open
011
OFF
ON
ON
External input
Open
Open
001
OFF
OFF
ON
Open
External input External input
Open External input
000
OFF
OFF
OFF
Open
SLS System Logic Semiconductor
SL20T0081
Figure 9. Power supply circuits for various voltage boosting
VCI
VDD
VCI
VDD
C1
+
C1
+
VCI VSS VOUT C4+ C3+ C1C1+ C2+ C2-
C1
+
C1
+ +
C1
VCI VSS VOUT C4+ C3+ C1C1+ C2+ C2-
(a) 2-times voltage boosting configuration (VOUT = 2VCI)
(b) 3-times voltage boosting configuration (VOUT = 3VCI)
VCI
VDD
VCI
VDD
C1
+
+
C1 C1
+ +
C1
VCI VSS VOUT C4+ C3+ C1C1+ C2+ C2-
C1
+ +
C1
+
C1 C1
+ +
C1
VCI VSS VOUT CAP4+ CAP3+ CAP1CAP1+ CAP2+ CAP2-
(c) 4-times voltage boosting configuration (VOUT = 3VCI)
(d) 5-times voltage boosting configuration (VOUT = 5VCI)
SLS System Logic Semiconductor
SL20T0081
Voltage Regulator Circuits The function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, V0,by adjusting resistors, Ra and Rb, within the range of [V0]< [VOUT]. Because VOUT is the operating voltage of operational amplifier circuits showing Figure 10, it is necessary to be applied internally or externally. For the Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra are connected internally or externally by INTRS pin. And VEV called the voltage of electronic volume is determined by Eq. 2,, where the parameter is the value selected by o instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta = 25 C is shown in table 9. V0 = ( 1 + Rb ) x VEV [V] Ra (63 - ) ) x VREF [V] 162 (Eq.1)
VEV = ( 1 -
(Eq.2)
Table 9. VREF Voltage at Ta = 25 C REF H L Temp. coefficient -0.05% / C External input
o
o
VREF [V] 2.1 VEXT
Table 10. Electronic Contrast Control Register (64 Steps) VR5 0 0 : : 1 : : 1 1 VR4 0 0 : : 0 : : 1 1 VR3 0 0 : : 0 : : 1 1 VR2 0 0 : : 0 : : 1 1 VR1 0 0 : : 0 : : 1 1 VR0 0 1 : : 0 : : 0 1 Reference voltage parameter 0 1 : : 32(default) : : 62 63 Minimum Low V0 Contrast
: : : : : :
: : : : : :
Maximum
High
SLS System Logic Semiconductor
SL20T0081
Figure 10. Internal Voltage Regulator Circuit
VOUT VOUT
+ + VEV -
Internal Regulator Resistors (Ra, Rb)
External Regulator Resistors (Ra', Rb') V0
Rb
Rb'
VR Ra Ra'
VSS
GND
SLS System Logic Semiconductor
SL20T0081
In Case of Using Internal Resistors, Ra and Rb (INTRS = "H") When INTRS pin is "H", resistor Ra is connected internally between VR pin and VSS, and Rb is connected between V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Table 11. Internal Rb/Ra ratio depending on 3-bit data (R2 R1 R0) R2 R1 R0 1 + ( Rb/Ra ) 000 3.0 001 3.5 010 4.0 011 4.5 100 5.0 101 5.5 110 6.0 111 6.4
The following figure shows V0 voltage measured by adjusting internal regulator resistor ratio (Rb/Ra) and 6-bit o electronic volume registers for each temperature coefficient at Ta = 25 C. Figure 11. Electronic Volume Level V0[V] 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 0 8 16 24 32 40 48 56 Electronic Volume level R2 R1 R0 (1 1 1) (1 1 0) (1 0 1) (1 0 0) (0 1 1) (0 1 0) (0 0 1) (0 0 0)
SLS System Logic Semiconductor
SL20T0081
In Case of Using External Resistors, Ra and Rb (INTRS ="L") When INTRS pin is "L", it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0 and VR.
Example : For the following requirements 1. LCD driver voltage, V0 = 10V 2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. Maximum current flowing Ra, Rb = 1uA
From Eq.1 and Eq.2 10 = ( 1 + Rb Ra ) x VEV [V] (Eq.3)
VEV = ( 1 -
(63 -32 ) 162
) x 2.1 1.698 [V]
(Eq.4)
From requirement 3 10 Ra + Rb = 1 [uA] (Eq.5)
From equations Eq.3, 4 and 5 Ra 1.69 [M] Rb 8.31 [M] The following table shows the range of V0 depending on the above requirements. Table 12. V0 Depending on Electronic Volume Level Electronic volume level 0 V0 7.57 ... ... ... ... 32 10.00 ... ... ... ... 63 12.43
SLS System Logic Semiconductor
SL20T0081
Voltage Follower Circuits VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3, V4), and those output impedance are converted by the Voltage Follower for increasing drive capability. The following table shows the relationship between V1 to V level and each duty ratio. Table 13. The Relationship between V1 to V4 Level and Duty Ratio Duty ratio DUTY2 H H DUTY1 L H DUTY0 L H LCD bias 1/8 1/10 1/7 1 / 65 L L H 1/9 1/6 1 / 55 L L H 1/8 1/6 1 / 49 L L H 1/8 1/5 1 / 33 L L H 1/6 (5/6) xV0 (5/6) x V0 (2/6) x V0 (1/6) x V0 (7/8) xV0 (4/5) x V0 (6/8) x V0 (3/5) x V0 (2/8) x V0 (2/5) x V0 (1/8) x V0 (1/5) x V0 (7/8) xV0 (5/6) x V0 (6/8) x V0 (4/6) x V0 (2/8) x V0 (2/6) x V0 (1/8) x V0 (1/6) x V0 (8/9) x V0 (5/6) x V0 (7/9) x V0 (4/6) x V0 (2/9) x V0 (2/6) x V0 (1/9) x V0 (1/6) x V0 V1 (7/8) x V0 (9/10) x V0 (6/7) x V0 V2 (6/8) x V0 (8/10) x V0 (5/7) x V0 V3 (2/8) x V0 (2/10) x V0 (2/7) x V0 V4 (1/8) x V0 (1/10) x V0 (1/7) x V0
1 / 81
High Power Mode
The power supply circuit equipped in the SL20T0081 for LCD drive has very low power consumption (in normal mode: HPMB = "H"). If use for LCD panels with large loads, this low-power power supply may cause display quality to degrade. When this occurs, setting the HPMB pin to "L" (high power mode) can improve the quality of the display. Moreover, if the quality of display is inadequate even after high power mode has been set, then it is necessary to add a liquid crystal drive power supply externally ( VOUT or V0 or V1, V2, V3, V4 ).
SLS System Logic Semiconductor
SL20T0081
RESET CIRCUIT
Setting RESET to "L" or Reset instruction con internal function. When RESET becomes "L", following procedure is occurred. Display ON/OFF: OFF All segments ON/OFF: OFF(normal) ADC select: OFF(normal) Reverse display ON/OFF: OFF(normal) Power control register (VC, VR, VF) = (0,0,0) Serial interface internal register data clear LCD bias ratio: 1/9 (1/65 duty), 1/8 (1/55 duty), 1/6 (1/33 duty) On-chip oscillator OFF Power save release Read-modify-write: OFF SHL select: OFF(normal) Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) Display start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (1, 0, 0) Reference voltage set: OFF Reference voltage control register: (VR5, VR4, VR3, VR2, VR1, VR0) = (1, 0, 0, 0, 0, 0) Test mode release When RESET instruction is issued, following procedure is occurred. Read-modify-write: OFF Static indicator mode: OFF Static indicator register:(S1, S0) = (0, 0) SHL select: 0 Display start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (1, 0, 0) Reference voltage control register: (VR5, VR4, VR3, VR2, VR1, VR0) = (1, 0, 0, 0, 0, 0) Test mode release While RESET is "L" or Reset instruction is executed,no instruction except read status could be accepted. Reset status appears at D4. After D4 becomes "L", any instruction can be accepted. RESET must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESET is essential before used.
SLS System Logic Semiconductor
INSTRUCTION DESCRIPTION
Table 14. Instruction Table
Instruction Code Instruction RS Display ON/OFF Display start line set Display start line set (double byte instruction) Display start line reset N-line inversion (double byte instruction) N-line inversion reset Set page address Set column address MSB Set column address LSB Read status Write display data Read display data 0 0 0 0 0 0 0 0 0 0 0 0 1 1 RD WR 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 D7 1 0 1 x 1 1 x 1 1 0 0 BUSY D6 0 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0 DON
SL20T0081
Function DON = 1 : LCD display ON DON = 0 : LCD display OFF Set the Display Data RAM address that corresponds COM0 output Set the Display Data RAM address that corresponds COM0 output for 1/81 duty (7bits). Reset the Display Start line. Set the Display Data RAM address that corresponds COM0 output for 1/81 duty (7bits). Reset the N-line inversion. (N-line inversion disable) Set the page address Set the column address MSB Set the column address LSB Read device internal status Write data into display RAM Read data from display RAM Set SEG output direction ADC = 0 : SEG0 SEG131 ADC = 1 : SEG131 SEG0 Set display mode REV = 0 : normal display REV = 1 : reverse display Set display mode AON = 0 : normal display AON = 1 : display all segments ON Select LCD bias Read-modify-write mode enable Read-modify-write mode disable Initialize the device Set COM output direction COD = 0 : COM0 COM63 COD = 1 : COM63 COM0 BE RE FE : voltage booster enable : voltage regulator enable : voltage follower enable
SL5 SL4 SL3 SL2 SL1 SL0
0 1 0 1 0 0 1 SL6 SL5 SL4 SL3 SL2 SL1 SL0 0 0 x 0 0 0 0 1 1 x 1 1 0 0 0 1 0 0 0
0 1 0 1 1 NL4 NL3 NL2 NL1 NL0 0 1 1 0 1 P3 A7 A3 0 P2 A6 A2 0 D2 D2 1 P1 A5 A1 0 D1 D1 0 P0 A4 A0 0 D0 D0
ONOFF 0 ADC RESET D6 D6 D5 D5 D4 D4 D3 D3
D7 D7
ADC set
0
1
0
1
0
1
0
0
0
0
ADC
Reverse display ON/OFF All segments ON/OFF LCD bias select Set read-modify-write (RMW) mode Clear read-modify-write (RMW) mode Reset Common output direction (COD) set
0
1
0
1
0
1
0
0
1
1
REV
0
1
0
1
0
1
0
0
1
0
AON
0 0 0 0
1 1 1 1
0 0 0 0
1 1 1 1
0 1 1 1
1 1 1 1
0 0 0 0
0 0 1 0
0 0 1 0
1 0 1 1
BIAS 0 0 0
0
1
0
1
1
0
0
COD
x
x
x
LCD power setup
0
1
0
0
0
1
0
1
BE
RE
FE
X:Don't care
SLS System Logic Semiconductor
SL20T0081
Table 15. Instruction Table (continued)
Instruction Code Instruction RS Voltage regulator resistor ratio set Reference voltage register set (double byte instruction) Static segment driver ON (double byte instruction) Static segment driver OFF Power save control (compound instruction) NOP TEST TEST 0 0 0 1 1 1 0 0 0 1 1 1 1 1 0 1 1 0 0 1 1 0 X X 0 X X 0 0 0 0 0 0 RD WR 1 1 1 1 1 1 0 0 0 0 0 0 D7 0 1 x 1 x 1 D6 0 0 x 0 x 0 D5 1 0 D4 0 0 D3 0 0 D2 R2 0 D1 R1 0 D0 R0 1 Select internal resistor ratio of the voltage regulator (Rb/Ra) Select reference voltage to control display contrast. The static segment driver (FR-FRS) is enabled and display mode is controlled by 2'nd byte. The static segment driver is disabled Function
VR5 VR4 VR3 VR2 VR1 VR0 1 x 1 0 x 0 1 x 1 1 x 1 0 S1 0 1 S0 0
The device is entered power saving state when instructions set display off and all segments on. 0 X X 1 X X Non-Operation command Don't use this instruction Don't use this instruction
X:Don't care
SLS System Logic Semiconductor
SL20T0081
Display ON/OFF Turns the Display ON/OFF RS 0 RW 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 DON
DON =1 : display ON DON =0 : display OFF Display Start Line Set Sets the line address of display RAM to determine the Initial Display Line. The RAM display data is displayed at the top row (COM0 when SHL = L, COM63 when SHL = H) of LCD panel. RS 0 ST5 0 0 : 1 1 RW 0 ST4 0 0 : 1 1 D7 0 ST3 0 0 : 1 1 D6 1 ST2 0 0 : 1 1 D5 ST5 ST1 0 0 : 1 1 D4 ST4 ST0 0 1 : 0 1 D3 ST3 D2 ST2 D1 ST1 D0 ST0
Line address 0 1 : 62 63
Set Page Address Sets the Page Address of display data RAM from the microprocessor into the Page Address register. Any RAM data bit can be accessed when its Page Address and column address are specified. Along with the column address, the Page Address defines the address of the display RAM to write or read display data. Changing the page address doesn't effect to display status. RS 0 P3 0 0 : 0 1 1 1 RW 0 D7 1 P2 0 0 : 1 0 0 0 D6 0 D5 1 P1 0 0 : 1 0 0 1 D4 1 D3 P3 P0 0 1 : 1 0 1 0 D2 P2 D1 P1 Page 0 1 : 7 8 9 10 D0 P1
SLS System Logic Semiconductor
SL20T0081
Set Column Address Sets the Column Address of display RAM from the microprocessor into Column Address register. Along with the Column Address, the Column Address defines the address of the display RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, Column Addresses are automatically increased. Set Column Address MSB RS 0 RW 0 D7 0 D6 0 D5 0 D4 1 D3 A7 D2 A6 D1 A5 D0 A4
Set Column Address LSB RS 0 A7 0 0 : 1 1 RW 0 A6 0 0 : 0 0 D7 0 A5 0 0 : 0 0 D6 0 A4 0 0 : 0 0 D5 0 A3 0 0 : 0 0 D4 1 A2 0 0 : 0 0 D3 A3 A1 0 0 : 1 1 D2 A2 A0 0 1 : 0 1 D1 A1 D0 A0
Column address 0 1 : 130 131
Read Status Read the internal status of the SL20T0081. RS 0 RW 1 Flag D7 BUSY D6 ADC D5 ON/OFF D4 RESET D3 0 Description The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy Indicates the relationship between RAM column address and segment driver. 0: reverse direction (SEG131 SEGO), 1: normal direction (SEGO SEG131) Indicates display ON / OFF status. 0: display ON, 1: display OFF Indicates the initialization is progress by RESET signal. 0: chip is active, 1: chip is being reset D2 0 D1 0 D0 0
BUSY
ADC
ON/OFF
RESET
SLS System Logic Semiconductor
SL20T0081
Write Display Data 8-bit data of display data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. RS 1 RW 0 D7 D6 D5 D4 D3 D2 D1 D0
Write data
Figure 12. Sequence for Writing Display Data Set Page Address Set Column Address
Figure 13. Sequence for Reading Display Data Set Page Address Set Column Address
Dummy Data Read Data Write
Data Read YES Data Read Continue? YES NO Optional Status NO Optional Status Column address is increased automatically after Read or Write operation. Data Read Continue?
Read Display Data 8-bit data from display data RAM specified by the column address and page address can be read by this Instruction. As the column address is increased by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. A dummy read is required after loading an address into the column address register. Display data cannot be read through the serial interface. RS 1 RW 1 D7 D6 D5 D4 D3 D2 D1 D0
Read data
ADC Select (Segment Driver Direction Select) Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins can be reversed by software. This makes IC layout flexible in LCD module assembly. RS 0 RW 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 ADC
ADC = 0: normal direction (SEG0 SEG131) ADC = 1: reverse direction (SEG131 SEG0)
SLS System Logic Semiconductor
SL20T0081
Reverse Display ON / OFF Reverses the display status in LCD panel without rewriting the contents of the display data RAM. RS 0 REV 0 (normal) 1 (reverse) RW 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 REV
RAM bit data = "1" LCD pixel is illuminated LCD pixel is not illuminated
RAM bit data = "0" LCD pixel is not illuminated LCD pixel is illuminated
All segments ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the display data RAM.At this time, the contents of the display data RAM are held. This instruction has priority over the Reverse Display ON / OFF instruction. RS 0 RW 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0
D0 EON
EON = 0: normal display EON = 1: entire display ON Select LCD Bias Selects LCD bias ratio of the voltage required for driving the LCD. RS 0 Duty ratio 1/33 1/49 1/55 1/65 1/81 RW 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 LCD bias DUTY2 0 0 0 0 1 DUTY1 0 0 1 1 0 DUTY0 Bias = 0 0 1 0 1 0 1/6 1/8 1/8 1/9 1/10 Bias = 1 1/5 1/6 1/6 1/7 1/8 D1 1 D0 Bias
Set Read-Modify-Write This instruction stops the automatic increment of the column address by the read display data instruction,but the column address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Modify-read instruction. RS 0 RW 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0
SLS System Logic Semiconductor
SL20T0081
Reset Read-Modify-Write This instruction cancels the Read-Modify-Write mode, and makes the column address return to its initial value just before the set Read-Modify-Write instruction is started. RS 0 RW 0 D7 1 D6 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0
Figure 14. Sequence for Cursor Display
Set Page Address
Set Column Address (N)
Set Modify-Read
Dummy Read
Data Read
Data Process
Data Write
NO Chang Complete? YES Reset Modify-Read
Return Column Address
Reset This instruction resets initial display line, column address, page address, and common output status select to their initial status, but does not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply, which is initialized by the RESET pin. RS 0 RW 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0
SLS System Logic Semiconductor
SL20T0081
Common Output Direction (COD) set COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS 0 RW 0 D7 1 D6 1 D5 0 D4 0 D3 SHL D2 x D1 x D0 x X: Don't care
COD = 0: normal direction ( COM0 COM79 ) COD = 1: reverse direction ( COM79 COM0 )
Power Control Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS 0 VC 0 1 0 1 0 1 RW 0 VR D7 0 VF D6 0 D5 1 D4 0 D3 1 D2 VC D1 VR D0 VF
Status of internal power supply circuits Internal voltage converter circuit is OFF Internal voltage converter circuit is ON Internal voltage converter circuit is OFF Internal voltage converter circuit is ON Internal voltage converter circuit is OFF Internal voltage converter circuit is ON
Regulator Resistor Select Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. Refer to the table 15. RS 0 R2 0 0 0 0 1 1 1 1 RW 0 R1 0 0 1 1 0 0 1 1 D7 0 R0 0 1 0 1 0 1 1 0 D6 0 D5 1 D4 0 D3 0 (1+ Rb / Ra) ratio 3.0 3.5 4.0 4.5 5.0 (default) 5.5 6.0 6.4 D2 R2 D1 R1 D0 R0
1
SLS System Logic Semiconductor
SL20T0081
Reference Voltage Select st nd Consists of 2- byte instruction. The 1 instruction set reference voltage mode, the 2 one updates the contents of reference voltage register. After second instruction, reference voltage mode is released. The 1 Instruction : Set Reference Voltage Select Mode RS 0 RW 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1
st
The 2nd Instruction : Set Reference Voltage Register
RS 0 RW 0 D7 x D6 x D5 VR5 D4 VR4 D3 VR3 D2 VR2 D1 VR1 D0 VR0
VR5 0 0 : : 1 : : 1 1
VR4 0 0 : : 0 : : 1 1
VR3 0 0 : : 0 : : 1 1
VR2 0 0 : : 0 : : 1 1
VR1 0 0 : : 0 : : 1 1
VR0 0 1 : : 0 : : 0 1
Reference voltage parameter() 0
V0
Contrast
Minimum 1 : : 32 (default) : : 62 63 Maximum
Low
: : : : :
: : : : :
High
Figure 15. Sequence for Setting the Reference Voltage
Setting Reference Voltage Start
1st Instruction for Mode Setting
2nd Instruction for Register Setting
Setting Reference Voltage Start
SLS System Logic Semiconductor
SL20T0081
Set Static Indicator State Consists of two bytes instruction. The first byte instruction (set Static Indicator Mode) enables the second byte instruction (set Static Indicator Register) to be valid. The first byte sets the static indicator ON /OFF. When it is on, the second byte updates the contents of static indicator register without issuing any other instruction and this Static Indicator state is released after setting the data of indicator register. The 1 st Instruction : Set Static Indicator Mode (ON/OFF) RS 0 RW 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 0 D0 SM
SM = 0: static instruction OFF SM = 1: static instruction ON The 2 nd Instruction : Set Static Indicator Register RS 0 S1 0 0 1 1 RW 0 D7 x S0 0 1 0 1 D6 x D5 x D4 x D3 x D2 x D1 S1 D0 S0
Status of static indicator output OFF ON (about 1 second blinking) ON (about 0.5 second blinking) ON (always ON)
NOP Non Operation Instruction RS 0 RW 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1
Test Instruction (Test Instruction_1 &Test Instruction_2)
Thee are the instruction for IC chip testing. Please do not use it. If the test instruction is used by accident,it can be cleared by applying "0" signal to the RESET input pin or the reset instruction. RS 0 0 RW 0 0 D7 1 1 D6 1 0 D5 1 0 D4 1 1 D3 x x D2 x x D1 x x D0 x x
SLS System Logic Semiconductor
SL20T0081
Power Save (Compound Instruction) If the entire display ON/OFF instruction is issued during the display OFF state, SL20T0081 enters the Power Save status to reduce the power consumption to the static power consumption value. According to the status of static indicator mode, power save is entered to one mode of sleep and standby mode. When Static Indicator mode is ON, standby mode is issued. When OFF, sleep mode is issued. Power save mode is released by the entire display OFF instruction. Figure 16. Power Save (Compound Instruction)
Static Indicator OFF
Static Indicator ON
Power Save (compound Indicator) [Display OFF] [All segments ON]
Sleep Mode [Oscillator Circuit: OFF] [All COM/SEG Outputs: VSS] [Consumption Current:<2uA]
Standby Mode [Oscillator Circuit: OFF [LCD Power Supply Circuit: OFF] [All COM/SEG Outputs: VSS] [Consumption Current: <10uA]
Power Save OFF (Compound Instruction) [All segments OFF] [Static Indicator ON] 2 Bytes Command
Power Save OFF [All segments OFF]
Release Sleep Mode
Release Standby Mode
- Sleep Mode This stops all operations in the LCD display system, and as long as there are no access from the MPU, the consumption current is reduced to a value near the static current. The internal modes are as follows : a. The oscillator circuit and LCD power supply circuit are halted. b. All liquid crystal drive circuit are halted, and the segment in common drive outputs a VSS level. - Standby Mode The duty LCD display system operation are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. a. The LCD power supply circuits are halted. The oscillator circuit continues to operate. b. The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs a VSS level. The static drive system does not operate. When a reset command is performed while in standby mode, the system enter sleep mode.
SLS System Logic Semiconductor
SL20T0081
Referential Instruction Setup Flow (1) Figure 17. Initializing with the Built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization
Power ON (VDD - VSS) Keeping the RESET Pin = "L"
Waiting for Stabilizing the Power
RESET Pin ="H"
User Application Setup by Internal Instructions [ADC Select] [SHL Select] [LCD Bias Select]
User LCD Power Setup by Internal Instructions [Voltage Converter ON] Waiting for >1ms User LCD Power Setup by Internal Instructions [Voltage Regulator ON] Waiting for >1ms User LCD Power Setup by Internal Instructions [Voltage Follower ON]
User LCD Power Setup by Internal Instructions [Regulator Resistor Select] [Reference Voltage Register Set]
Waiting for Stabilizing
End of Initialization
SLS System Logic Semiconductor
SL20T0081
Referential Instruction Setup Flow (2) Figure 18. Initializing without the Built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization
Power ON (VDD - VSS) Keeping the RESET Pin = "L"
Waiting for Stabilizing the Power
RESET Pin ="H"
Set Power Save
User Application Setup by Internal Instructions [ADC Select] [SHL Select] [LCD Bias Select]
User LCD Power Setup by Internal Instructions [Regulator Resistor Select] [Reference Voltage Register Set]
Release Power Save
Waiting for Stabilizing
End of Initialization
SLS System Logic Semiconductor
SL20T0081
Referential Instruction Setup Flow (3) Figure 19. Data Display setup
End of Initialization
Display Data RAM Addressing by Instruction [Initial Display Line] [Set Page Address] [Set Column Address]
Write Display ON/OFF by Instruction [Display ON/OFF]
Turn Display ON/OFF by Instruction [Display ON/OFF]
End of Display setup
SLS System Logic Semiconductor
SL20T0081
Referential Instruction Setup Flow (4) Figure 20. Power OFF
Optional status
Turn Display ON/OFF by Instruction [Display OFF]
User LCD Power Setup by Internal Instructions [Voltage Regulator OFF] Waiting for >50ms User LCD Power Setup by Internal Instructions [Voltage Follower OFF] Waiting for >1ms User LCD Power Setup by Internal Instructions [Voltage Converter OFF] Waiting for >1ms Power OFF (VDD-VSS)
SLS System Logic Semiconductor
SL20T0081
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Table 16. Absolute Maximum Ratings Parameter Power supply voltage Power supply voltage Symbol VDD Unless otherwise noted, VSS = 0V Conditions -0.3 ~ +7.0 -0.3 ~ +7.0 -0.3 ~ +6.0 -0.3 ~ +4.5 V0, VOUT V1, V2, V3, V4 VIN VO TOP TCP Bare chip TST -0.3 ~ +18.0 -0.3 ~ V0 -0.3 ~ VDD + 0.3 -0.3 ~ VDD + 0.3 -40 ~ + 85 -55 ~ + 100 -55 ~ + 125 Unit V V
With Triple step-up With Quad step-up
Power supply voltage(3) Power supply voltage(4) Input voltage Output voltage Operating temperature Storage temperature
V V V V
o
C C
o
Figure 21. Relations between powers and V voltages
V0, VOUT
V1 ~ V4 VCC VDD
GND System (MPU)side
VSS SL20T0081 side
NOTES : 1. VDD and VLCD are based on VSS = 0V. 2. Voltages V0 > V1> V2 > V3 > V4 > VSS must always be satisfied. (VLCD = V0 - VSS) 3. If supply voltage exceeds its absolute maximum range,this LSI may be damaged permanently. It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result.
SLS System Logic Semiconductor
SL20T0081
DC CHARACTERISTICS
Table 17. DC Characteristics Item Symbol Unless otherwise specified, VSS = 0V, VDD = 3.0 V 10%, Ta = -40 to 85C Condition Condition Min. Operating Voltage Operating Voltage(2) High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input leakage current Output leakage current LCD driver output ON Resistance Internal Oscillator External Input Internal Oscillator External Input Internal Oscillator External Input Internal Oscillator External Input Internal Oscillator External Input VDD 2.4 Typ. Max. 5.5 V VDD Units Pin
V0 VIH VIL VOH VOL IIL VIN = VDD or VSS IOL RON fOSC 1/81 Duty, Ta = 25 C fCL fOSC 1/65 Duty, Ta = 25 C fCL fOSC 1/55 Duty, Ta = 25 C fCL fOSC 1/49 Duty, Ta = 25 C fCL fOSC 1/33 Duty, Ta = 25 C fCL Ta = 25 C V0 = 8V IOH = - 0.5mA IOL = 0.5mA
4.5 0.8 x VDD 0 0.8 x VDD 0 -1.0 -3.0 6.3 5.5 5 4.3 2.9 -
2.0 12.6 12.6 10.9 10.9 10.0 10.0 8.7 8.7 5.8 5.8
15.0 VDD 0.2 x VDD VDD 0.2 x VDD 1.0 3.0 3.0 18.9 16.4 15.0 13.0 8.7 -
V V V V V uA uA K kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz
V0
LCD drive pins
CL
CL
Oscillator Frequency
CL
CL
CL
SLS System Logic Semiconductor
SL20T0081
Table 18. DC Characteristics (continued) Item Symbol Condition
(VSS = 0V, VDD =2.4 to 3.6V, Ta =-40 to 85 C) Condition Units Min. x2 x3 2.4 2.4 2.4 2.4 Typ. Max. 3.6 3.6 V x4 x5 3.6 3.2 V Pin
o
Voltage converter input voltage
V
Voltage converter output voltage Voltage regulator operating voltage Voltage regulator operating voltage Reference voltage
VOUT
X2 /x3 /x4 /x5 voltage conversion (no-load)
95
99
-
%
VOUT
VOUT V0 VREF Ta=25 C (-0.05%/ C)
o o
6.0 4.5 2.04
2.1
16.0 15.0 2.16
V V V
VOUT V0 *9
SLS System Logic Semiconductor
SL20T0081
Table 19.
Dynamic Current Consumption (1) when the Built -in Power Circuit is OFF (At Operate Mode) Symbol Condition VDD =3.0V V0-VSS =11.0V 1/65 duty ratio Display pattern OFF Min. Typ. Max. Unit
(Ta =25 C) Pin used
o
Item Dynamic current consumption(1)
IDD1
-
15
23
A
*11
Table 20.
Dynamic Current Consumption (2) when the Built -in Power Circuit is ON (At Operate Mode) Symbol Condition VDD =3.0V (V =VDD,4 time boosting) V0-VSS =11.0V, 1/65 duty ratio, Display pattern OFF, Normal power mode Min. Typ. Max. Unit
(Ta =25 C) Pin used
o
Item
-
40
60
A
*12
Dynamic current consumption(2)
IDD2 VDD =3.0V (V =VDD,4 time boosting) V0-VSS =11.0V, 1/65 duty ratio, Display pattern checker, Normal power mode
-
150
200
A
*12
Table 21. Item
Current Consumption during Power Save Mode Symbol IDD1 IDD2 Condition During sleep During standby Min. Typ. Max. 2.0 10.0 Unit A A
(Ta =25 C) Pin used
o
Sleep mode current Standby mode current
SLS System Logic Semiconductor
SL20T0081
Table 22. The Relationship between Oscillation Frequency and Frame Frequency Duty ratio Item On-chip oscillator circuit is used 1/81 On-chip oscillator circuit is not used On-chip oscillator circuit is used 1/65 On-chip oscillator circuit is not used On-chip oscillator circuit is used 1/55 On-chip oscillator circuit is not used On-chip oscillator circuit is used 1/49 On-chip oscillator circuit is not used On-chip oscillator circuit is used 1/33 On-chip oscillator circuit is not used External input ( fCL ) External input ( fCL ) fOSC = 5.82 kHz External input ( fCL ) fOSC = 8.72 kHz External input ( fCL ) fOSC = 9.96 kHz External input ( fCL ) fOSC = 10.90 kHz fCL fOSC = 12.57 kHz fFR fOSC 2 x 2 x 81 fCL 2 x 2 x 81 fOSC 2 x 2 x 65 fCL 2 x 2 x 65 fOSC 2 x 2 x 55 fCL 2 x 2 x 55 fOSC 2 x 2 x 49 fCL 2 x 2 x 49 fOSC 2 x 2 x 33 fCL 2 x 2 x 33
(fosc:oscillation frequency, fCL: display clock frequency, fFR : LCD AC signal frequency)
[*Remark Solves] *1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the MPU. *2. In case of external power supply is applied. *3. CE1, CE2, RS, D7, to D0, RD(E), WR(R/W), RESET, MS, P68/80, PS, INTRS, HPMB, CLS, CL, SYNC, FR, DISP pins. *4. D0 to D7, SYNC, FR, DISP, CL pins. *5. CE1, CE2, RS, D7 to D0, RD(E), WR(R/W), RESET, MS, P68/80, PS, INTRS, HPMB,CLS, CL, SYNC, FR, DISP pins. *6. Applies when the DB[7:0], SYNC, FR, DISP, and CL pins are in high impedance. *7. Resistance value when C0.1[mA] is applied during the ON status of the output pin SEGn or COMn. RON =UV / 0.1 [ka] (UV : voltage change when C0.1[mA] is applied in the IN status.) *8. See table 22 for the relationship between oscillation frequency and frame frame frequency. *9. The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range *10 . On-chip reference voltage source of the voltage regulator circuit to adjust V0. *11,*12. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built-in power supply circuit is ON or OFF. The current flowing through voltage regulation resistors (Ra and Rb) is not included. It does not include the current of the LCD panel capacity, wiring capacity, etc.
SLS System Logic Semiconductor
SL20T0081
AC CHARACTERISTICS
Figure 22. Read/Write Characteristics (8080-series Microprocessor)
RS tAS CE1 (CE2 = 1) 0.9VDD tCY tPW(R), tPW(W) RD, WR 0.1VDD tDS D7 ~ D0 (Write) tACC D7 ~ D0 (Read) tOD tDH tAH
Table 23. Read/Write Characteristics (8080-series Microprocessor) Item Address setup time Address hold time System cycle time Pulse width (R) Pulse width (W) Data setup time Data hold time Read access time Output disable time Signal RS RS E(RDB) E(RDB) D7 to D0 Symbol tAS tAH tCY tRD tWR tDS tDH tACC tOD Min. 0 0 300 60 60 40 15 10 Typ. -
(VDD = 2.4 to 3.6V, ta = -40 to +85 C) Max. 140 100 Unit ns ns ns ns ns ns CL = 100pF Remark
o
SLS System Logic Semiconductor
SL20T0081
Figure 23. Read/Write Characteristics (6800-series Microprocessor)
RS tAS CE1 (CE2 = 1) 0.9VDD tCY tPW(R), tPW(W) E 0.1VDD tDS D7 ~ D0 (Write) tACC D7 ~ D0 (Read) tOD tDH tAH
Table 24. Read/Write Characteristics (6800-series Microprocessor) Item Address setup time Address hold time System cycle time Pulse width (R) Pulse width (W) Data setup time Data hold time Read access time Output disable time Signal RS RS E(RDB) E(RDB) D7 to D0 Symbol tAS tAH tCY tRD tWR tDS tDH tACC tOD Min. 0 0 300 120 60 40 15 10 Typ. -
(VDD = 2.4 to 3.6V, ta =-40 to +85 C) Max. 140 100 Unit ns ns ns ns ns ns CL = 100pF Remark
o
SLS System Logic Semiconductor
SL20T0081
Figure 24. Serial Interface Characteristics tCSS CE1 (CE2 = 1) tASS RS tCYS D6 (SCK) 0.1VDD tWLS tDSS D7 (SI) tDHS 0.9VDD tWHS tAHS tCHS
Table 25. Serial Interface Characteristics Item Serial clock cycle SCLK high pulse width SCLK low pulse width Address setup time Address hold time Data setup time Data hold time CE1 setup time CE1 hold time Signal D6 (SCLK) Symbol tCYS tWHS tWLS tASS tAHS tDSS tDHS tCSS tCHS Min. 250 100 100 150 150 100 100 150 150 Typ. -
(VDD = 2.4 to 3.6V, ta =-40 to +85 C) Max. Unit Remark
o
ns
RS D7 (SID) CE1
ns
ns
ns
SLS System Logic Semiconductor
SL20T0081
Figure 25. Reset Input Timing tRESETB RESET tIRST Internal reset operation
Table 26. Reset Input Timing Item RESET low pulse width Reset time Signal RESET Symbol tRESETB tIRST Min. 30.0 Typ. -
(VDD = 2.4 to 3.6V, ta =-40 to +85 C) Max. 60.0 Unit ns ns Remark
o
Figure 26. Display Control Output Timing tDFR CL
FR
Table 27. Display Control Output Timing Item FR delay time Signal FR Symbol tDFR Min. Typ. 20
(VDD = 2.4 to 3.6V, ta =-40 to +85 C) Max. 80 Unit ns Remark CL=50pF
o
SLS System Logic Semiconductor
REFERENCE APPLICATIONS
LCD power supply configuration
Example 1 : When using internal LCD power circuit (4-time voltage boost / VCI = VDD)
VDD VDD
SL20T0081
C1
C1 C1
C1
MS VCI VSS VOUT C4+ C3+ C1C1+ C2+ C2VR
+ + + + +
IRE
C1
C1 C1
C1 Ra Rb
MS VCI VSS VOUT C4+ C3+ C1C1+ C2+ C2VR
+ + + + +
IRE
VSS
C2 C2 C2 C2 C2
-
V0 V1 V2 V3 V4 VSS
C2 C2 C2 C2 C2
-
V0 V1 V2 V3 V4
VSS
(a) Using internal voltage regulator resistors (IRE=1) Example 2
(b) Using external voltage regulator resistors (IRE=0)
: Using Internal LCD power circuit (not using voltage booster circuit)
VDD VDD
MS VCI External Power Supply VOUT C4+ C3+ C1C1+ C2+ C2VR
+ + + + +
IRE VCI External Power Supply
MS
IRE
VSS
Ra Rb
VOUT C4+ C3+ C1C1+ C2+ C2VR
+ + + + +
C2 C2 C2 C2 C2 -
V0 V1 V2 V3 V4 VSS
C2 C2 C2 C2 C2 -
V0 V1 V2 V3 V4
VSS
(c) Using internal voltage regulator resistors (IRE=1)
(d) Using external voltage regulator resistors (IRE=0)
SLS System Logic Semiconductor
SL20T0081
Example 3
: Using Internal LCD power circuit (Only use voltage follower circuit)
VDD
External Power Supply
MS VCI VSS VOUT C4+ C3+ C1C1+ C2+ C2VR
+ + + + +
IRE
C2 C2 C2 C2 C2 -
V0 V1 V2 V3 V4
Example 4
: Using External LCD power supply
VDD
MS VCI VOUT C4+ C3+ C1C1+ C2+ C2VR V0 V1 V2 V3 V4
IRE
External Power Supply
SLS System Logic Semiconductor
SL20T0081
Data transfer interface
Figure 27. Data transfer interface
6800 series MPU
CE1 CE2 RS E RW D7~D0 RESET VDD VDD
CE1 SL20T0081 CE2 RS RD(E) WR(R/W) D7~D0 RESET P68/80 PS
(a) 6800 Bus type interface
8080 series MPU
CE1 CE2 RS RD WR D7~D0 RESET VSS VDD
CE1 SL20T0081 CE2 RS RD(E) WR(R/W) D7~D0 RESET P68/80 PS
(b) 8080 Bus type interface
MPU
CE1 CE2 RS SI SCK RESET VDD or VSS VSS
CE1 SL20T0081 CE2 RS D7 D6 D5~D0 RESET P68/80 PS
(c) Serial interface

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